It strikes me, that it would be worth putting one of those single gate
Schmitt trigger chips at the clock input of each of the offending chips.
Then you could have a slow rise time clock distributed around the PCB,
with a Schmitt trigger to smarten the edge up and deal with any noise on
the distribution line. For the amount of effort going into attempting to
make a fast device with non-Schmitt input deal with a slow and
potentially noisy waveform, everyone is hand waving madly and getting
nowhere.

TIs Little Logic and the similar Fairchild line are what I am thinking
of.


> -----Original Message-----
> From: piclist-bounces@mit.edu [mailto:piclist-bounces@mit.edu] On
Behalf Of
> RussellMc
> Sent: 30 June 2010 03:06
> To: Microcontroller discussion list - Public.
> Subject: Re: [EE] Slew Rate Limited Clock Buffer?
> 
> > >> It can violate specs for the M25P16V clock input. The
> > >> manual says the input signal slew rate can't be less
> > >> than 0.1 V/nsec
> 
> > http://www.numonyx.com/Documents/Datasheets/M25P16.pdf
> >
> > Table 15. AC characteristics (110 nm technology)
> > tCLCH Clock Rise time
> > tCHCL Clock Fall time MIN 0.1 V/ns expressed in slew rate.
> 
> Excellent. Some real data :-).
> Fig 23 shows the relationship of some of the relevant timings.
> So that's notionally about 30 nS clock slew time at 3V, so you'd want
> to keep well clear of that.
> That certainly does put a significant upper limit to the amount of
> "softening" that you can do on the line.
> 
> Possibly also relevant is a 2 ns minimum data setup time and a 5
> nanosecond data hold time. It MAY get to the stage where you need to
> see if any of these are being violated by undesired signal levels.
> There are a number of other relative timing relationships shown in the
> various diagrams which MIGHT get violated by ringing. When operating
> near the edge you'd need to go over all these to ensure that all were
> liable to be met.
> 
> In summary:
>        You say - making it work properly is best.
>         I say - Agreed, if you can do it.
> 
> There comes a stage where you have to do it, no matter how hard, and
> these rather unforgiving specs combined with multiple parts does push
> you towards needing to do it right. As you said :-).
> 
> Harold hasn't said if there is in fact a ground plane or parallel
> track under the relevant signal tracks at all locations. It looks like
> it's liable to be a good idea.
> 
> 
> 
>    Russell
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