> So, yes, the 1.5 ns was 'probably a bit low', but the
> 10 ns could not be relied if you NEED a slow rise time.

You don't "NEED a slow rise time".
30 ns is MAX allowed on M25P16 end of the line and 10 ns IS POSSIBLE
on PIC side. According to your logic10 ns on PIC side could easily
transform to 30 ns on M25P16 side of the line :-) (30 ns is MAX Clock
Rise time spec for M25P16 at 3V)

Don't slow down the clock edge, instead try to design the line so that
the edge guaranteed not to slow down less than 0.1 V/ns.

> It's engineering:
>
>  1.5 = 2
>  2 ~= 5 typical
>  2 ~~= 10 max
-- 
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist