> It doesn't matter *which* edge of the clock gets glitched -- a glitch
> is a glitch, and the extra clock pulse will still mess up the logic
> between the master and the slave.

This MAY be an extremely relevant point here.
IF you are in fact getting negative clock edge glitching and IF clock
and data are changed nominally simultaneously it may take only
extremely small reflections or power supply spikes or whatever to
produce double clocking.

A quickish and easyish check is to move the clock transition earlier
in time to, say,  about 1/4 way through cycle (rather than 1/2 way at
present) so that you have substantial data hold time after the clock
falls. This eliminates any effects of data to clock coupling.


            Russell
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