Em 26/6/2010 03:56, Marechiare escreveu:
>>> Your entire concept may probably be wrong. The problem is not
>>> reflections, it could be just PIC32 outputs are too weak to drive the
>>> line, so that your line "rings".  A synchro signal should be fast and
>>> should not "ring".  The answer in this case could simply be some
>>> output buffer (say FET) and a resistor (sort of 200 Ohm) at the line's
>>> end.
>>>       =

>> While I agree that 4mA may be a little wimpy, wouldn't a weak drive
>> have the opposite effect? As in, higher drive strength =3D sharper edges
>> =3D more parasitic effects?
>>     =

> Sorry, PIC32 I/O pins are 18 mA/18 mA current sink/source. Where did I
> get 4mA? I don't know. Still, 18 mA at 3 V means approx 100 Ohm output
> impedance. What's the point of placing 33 Ohm resistor in series with
> it? You need SPI clock signal edge as sharp as possible for said 100
> Ohm output impedance.
>
> Not only sharp, it should also be in-phase with the Data signal. The
> Clock and Data lines should be quite identical. I don't see how that
> could be done cheaply for multiple SPI recipients sitting on the same
> lines at 75 MHZ.
>   =



You don't need the data and clock to be "in-phase". Probably the SPI
master is changing the data line during the clock fall and the slave is
latching it during the clock rise.

Your clock edges can be slow. All you need to ensure is that the clock
"low" and "high" times meet a minimum (stated in the slave device
data-sheet), and there is enough time for the "data setup" and "data
hold" (also in the data-sheet) between the data transitions and the
slave detection of the clock changes.

In other words: Your data must be stable for a certain minimum time
before the slave "detects" the clock rise, and the data must remain
stable for another certain minimum time after the clock rise. Outside
this "window", the data may do whatever it wants.

The more "trapezoidal" your clock is, the better, as long as you don't
violate the AC timing parameters (including maximum clock rise and fall
times of course).

Isaac

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