Michael Wirth ha scritto:

> 
> I running a PIC 18F4320 at 40 MHz using a 10 MHz crystal and the HSPLL
> clock mode.  I have another chip on my board (quadrature encoder) that
> requires a sampling frequency clock somewhere between 10 KHz and 100
> KHz (TBD later).  Thought I could use one of the timers and a digital
> I/O line to generate this clock in software.  Thus setup Timer1 to
> interrupt every 50 microsec., down to every 5 microsec., to toggle the
> I/O line.


You  can probably optimize your ISR code and reach down to the 5uS 
required and less (if no other tests for IRQ are needed in the same 
handler).
But, I would use a PWM output for your goal: have you considered that?

-- 

Ciao, Dario
--
Cyberdyne
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