> > When the enable line is low the device looks like an on PFET in
> > series with battery. At this stage the device drwas 1 uA. Current
> > able to be drawn is probably limited by PFET rating. 500 mA or
> > 800 mA or whatever

> Yes, that's what I'd like to believe what they mean by "bypass",
> and it's common sense to expect that. I just found the explanation
> a little fuzzy and incomplete

The design makes it easy for them.
The output rectifier diode is a PFET.
When the chip is disabled:

- In one version they disable the FET and you get output isolation.

- In the other version they enable it and you get a through connection.

There is a possible "gotcha" here - BUT they may have very
specifically avoided it.
With a "normal" P MOSFET as the synchronous rectifier you would have a
reverse body diode which caused interesting results whichever way it's
connected under certain conditions.
eg the norm is to have the body diode in the same direction as it
would be if a conventional eg Schottky diode was used for output
(cathode to output). This means that you then do not get battery
cutoff by turning off the PFET.

>From their block diagram it appears that the body diode is absent - on
reflection this is probably the case with all synchronous rectifier
ICs with this topology and I have never looked into it. The FET is a
truly isolated one, unlike discrete units which have the substrate
implicitly connected to Drain by virtue of the means of construction.
Something new every day ... :-). Someone may care to correct me on
this.


     Russell
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