Hi all, I'm planning to transition a project to the PIC32MX695F512H chip. One feature I would like to use is the parallel port. In the datasheet (http://ww1.microchip.com/downloads/en/DeviceDoc/61156c.pdf), there are two conflicting bits of information: in the device pin diagram (page 9), pins 29 and 30 list PMA0/1 (address bits 0 and 1 of the parallel bus) as well as PMALL and PMALH (bits used to control external latches to use the low 8 data bits instead of the address bits to drive the address bus). So far, so good. However, in the feature-specific pin listing (page 30), it is indicated that PMA0 and PMA1 do not exist on 64-pin devices, while PMALL and PMALH (which are the same pins) do. So who's right? - Marcel -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist