This is a multipart message in MIME format. ------=_NextPart_000_006D_01CAE3CA.64CA02E0 Content-Type: multipart/related; boundary="----=_NextPart_001_006E_01CAE3CA.64CA02E0" ------=_NextPart_001_006E_01CAE3CA.64CA02E0 Content-Type: multipart/alternative; boundary="----=_NextPart_002_006F_01CAE3CA.64CA02E0" ------=_NextPart_002_006F_01CAE3CA.64CA02E0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Oaldog, The datasheet would be the first place I'd look. It shows what each of the bits represent, and what the logic value of each bit is to achieve that end. You didn't say what part you are using, but looking at the document below, and decoding the "3FF0" for the 16F877, would mean .... Hope this helps you see how the bits are decoded. Regards, Jim PIC16F877 has the special area to say Configuration Word in the program memory. This word is mapped in program memory location 2007h. This address is beyond the user program memory space. This word can be accessed only during programming. The following system requirements of PIC can be designated by the configuration word. http://www.piclist.com/images/www/hobby_elec/gif/pic7_61.gif 13, 12 = 11 = Code Protection Off 11 = 1 = ICD Disabled 10 = 1 = Not Used (See note below) 9 = 1 = Unprotected program memory may be written to by EECON control 8 = 1 = Code protection off 7 = 1 = RB3/PGM pin has PGM function, low voltage programming enabled 6 = 1 = BOR : BrownOut Reset Enabled 5, 4 = 11 = Same setting as bits 13, and 12 above (Code Protect Off) 3 = 0 = Power Up Timer Enabled 2 = 0 = Watch Dog Timer Disabled 1, 0 = 00 = Low Power Crystal oscillator ( Less than 200KHz ) Configuration Bits of PIC16F877 PIC16F877 has the special area to say Configuration Word in the program memory. This word is mapped in program memory location 2007h. This address is beyond the user program memory space. This word can be accessed only during programming. The following system requirements of PIC can be designated by the configuration word. CP1,CP0 : Flash Program Memory Code Protection Bits. (Bits 13 and 12) All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed. 11 : Code protection off 10 : 1F00h to 1FFFh code protected 01 : 1000h to 1FFFh code protected 00 : 0000h to 1FFFh code protected ---------------------------------------------------------------------------- ---- DEBUG : In-Circuit Debugger Mode (Bit 11) 1 : In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins. 0 : In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger. ---------------------------------------------------------------------------- ---- Bit 10 Not used. Not sure what part you are using, so can't tell if this would read as a '1' or '0' But for our purposes here, we'll say it reads as a '1' so it can illustrate the '3FF0' you refer to. ---------------------------------------------------------------------------- ---- WRT : Flash Program Memory Write Enable (Bit 9) 1 : Unprotected program memory may be written to by EECON control 0 : Unprotected program memory may not be written to by EECON control ---------------------------------------------------------------------------- ---- CPD : Data EEPROM memory Code Protection (Bit 8) 1 : Code protection off 0 : Data EEPROM memory code protected ---------------------------------------------------------------------------- ---- LVP : Low Voltage In-Circuit Serial Programming Enable bit (Bit 7) 1 : RB3/PGM pin has PGM function, low voltage programming enabled The high voltage programming mode is always available, regardless of the state of the LVP bit. 0 : RB3 is digital I/O, High Voltage on MCLR must be used for programming ---------------------------------------------------------------------------- ---- BODEN : Brown-out Reset Enable bit 1 : BOR enabled 0 : BOR disabled ---------------------------------------------------------------------------- ---- PWRTE : Power-up Timer Enable bit 1 : PWRT disabled 0 : PWRT enabled ---------------------------------------------------------------------------- ---- WDTE : Watchdog Timer Enable bit 1 : WDT enabled 0 : WDT disabled ---------------------------------------------------------------------------- ---- FOSC1,FOSC0 : Oscillator Selection bits 11 : RC : Resistor/Capacitor oscillator ( Less than 1MHz ) 10 : HS : High Speed Crystal/Resonator oscillator ( 4MHz to 20MHz ) 01 : XT : Crystal/Resonator oscillator ( Less than 4MHz ) 00 : LP : Low Power Crystal oscillator ( Less than 200KHz ) -----Original Message----- From: piclist-bounces@MIT.EDU [mailto:piclist-bounces@MIT.EDU] On Behalf Of Oaldog_Nutrix Sent: Saturday, April 24, 2010 3:20 PM To: piclist@MIT.EDU Subject: [PIC] pic config settings explanation wanted I'm new to pics. Whilst I understand the principles of the code, I'm having difficulty getting the head around the config settings in the header. I'm working from 2 books and with a Velleman Kit programmer. I know I have to declare the settings in the header but I'm confused by what appears to be conflicting information from the sources I've explored. One of the books simply gives a "standard" header and uses it over and again whilst the other glibly states that "H'3FF0' sets up LP OSC, WDT OFF, PUT ON, CP OFF. I know that '3FF0' equals 11111111110000 in binary and I think I know that these set the various bits. However, suppose I don't want LP OSC, WDT OFF. Which bits do what??? The values for int R/C Osc, Int Pullups ON/Off, etc continue to elude me. Can anyone suggest an "Idiot's guide" to explain in low-level terms how to set the configs? -- View this message in context: http://old.nabble.com/pic-config-settings-explanation-wanted-tp28336501p2833 6501.html Sent from the PIC - [PIC] mailing list archive at Nabble.com. -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist ------=_NextPart_002_006F_01CAE3CA.64CA02E0-- ------=_NextPart_001_006E_01CAE3CA.64CA02E0 Content-Type: image/gif; name="image001.gif" Content-Transfer-Encoding: base64 Content-ID: R0lGODdhTgIsALMAAAAAAIAAAACAAICAAAAAgIAAgACAgMDAwICAgP8AAAD/AP//AAAA//8A/wD/ /////ywAAAAATgIsAAAE//DJSau9OOvNu/9gKI5kaZ5oqq5s675wLM90bd94ru987//AoHBILBqP yKRyyWw6n9CodEqtWq/YrHbL3QEsgC9MTAnHyOUxGD1my8y1sNzdts3h8Rs+Tj/j9nxsYn0mchWD LoZlgCmKE4h+D4QskH95kpc6k5QSmyuVb4yRnolpjy9oqagXpCOqp6uwkZ05rYWmb162t7KzmJkz r3q4vy3CxZxgar27IMextMM0z9B/zSTUpb25wNcnhN4c4NXbn8Th4sTV6K7AeaJq7Ni1dvXlwRjy GX36+azL0QIaUxern7N3BsWBypXQQ8MODzVE9HeP2yJfBFXQmYgsm8ZOHP8PhaQ4bSFAZMtGitQk bVpGi4dOVmz0b91LjV9U/tJ5c+BMmQXptXTni+fNiW5Gbjzp0WfRoTCN/qQp0J5LS92ECkSqDGNV c8yY4psKNivWM3eufgU6Vi1Kt015kf1WU9tWsVGtwt2r96nbvn6hmvw4l25Xu9GUrtUmVepOe46N DkYMlZvjr/CogpxDbjGKpDozJ4pcK/LlxpLTEg3VpbXr17Bjy55Nu7bt27hz697Nu7fv38CDCx9O vDiTO8iTK1/OvLnz59CjS59Ovbr169iza9/Ovbv37+DDix9P/pCC8+jTq1/Pvr16AO7jy5cPf779 +woAHNjPv7///wAG2F//ffgV2B6BBiZ4HoIKJshggwU+CKF9Ek44X4UWxodhhuxtyOF6Hn6YniAi 3hdiifmheKGALLbI4oklwvihjDOqSJ+N7tHIoY4Z8jihjz/imKN5QnZYpJFHvufikkweACSETyoY pZRJvlclelM6eCWWW6bYZZYGkkhfGAvKMSJ+IZqZn5projkimWWaOceCXK6JoX5N5hmgh/D1aWd9 d1A4JqBqsnnhjWfSOaegb8JpZ5xYzkmghHzCuSidJl5oKZuOHhpneIla6Senkl6KZKSFOkoqgnc2 uumkqsaqIZE5cjlpmW5qaOuuXnqKKaBWKsprr0rqaeyAN45aJ7GIHjis/5/M1qprqNBGeyqmKd4K LLOWXgvis7hmOm22vMIIZoRGKkvsrYwui2218IZ7LYPagrtth7Q6K+y7uUpL7r7mUsutve6OeOzB Tib7b68ybljvvtZ+Oy6/7DZLMcFvYhvqqfFqbDHHDHsZ8JfpLlzxyAU/bHLBG9OL8b935uvtyf3q uyy0KIfsMsTV5ojwsXySS7O4Nl/scdHewszyzC/3LHTSG4d8tL9IP5zzospiXaqhUQvbsdS+eswu q1BrvLPIUd8LoswSo0o20VUXOvW8tqbaLcQ+NznHwUGPamjDE//Jb9hJ48w11YLrXHe3Ts8t9t81 zyx3xG0rri7YaZb8Nf+snUp+N+Zlrzs56InGXMbHlEZe+cCUB2v0zYq32eHPxma+7dvtMi0w4asr ja7AKjt9eddph96762I7jny9lw8deLmwK1/87r+Gjvvg1Zc+5OnjNt468iDvfPWwr39dLO16H3pv xbwD7/qJQbet49nxqvxr6v56D3j3rI/v9crYQxz0sJcz1q3MeZWjX+x8hy/u5c9a+3ug+OB2u/fF rnNYQl+ebEdA1blPe7mDGvtCGDy09Q9/NtOfBz9Yp6vJzW+d4lyrSmbCAAZOgSV03PUWWD8dsg1E nyMe0joURHmFbVVkuhSpIoYnDS6Jg6QLIRDV9ii4EZFTS7vhqiD1KfPxZRFVU4tgjooou9w9CGdm +2IWDUc/U63ujLHinBDXNUUwcrGMDXxEl76nonOhyYlM8qMVjyRIKRKSZIg8Gho7+LFDJvJKYtpS IdtXpCYC8kV7nOTzHCnJR1ZphwxE4BArmclM/pCUnkySJS+5p1J2MpWc/KQrFVnDk7lRjX2cJSRP KSRNbrKSrGyRLwWIylcaU5awLCYyj/lJXuJomKMEZjAFBE3j5TKZvcTmM3WpSm6q0pk2qubxpDlN AIkTfLFcJiS1GU5vKlOdzVwEeeZJz3ra8574zKc+98nPfvrzn9IxjkAHStCCGvSgCE2oQgsaAQA7 ------=_NextPart_001_006E_01CAE3CA.64CA02E0-- ------=_NextPart_000_006D_01CAE3CA.64CA02E0 Content-Type: image/gif; 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