Problem solved.

My interrupt service latency was long enough on some passes that TMR2 
could get to 0xff value at or just after loading the new CCPR2L value 
but before reenabling the counter. This caused the output compare to 
happen prematurely, and was consistent with the seemingly random nature 
of the glitch while having some coupling to interrupt services. It 
wasn't totally random because TMR2 was getting reset inside the ISR.
I now clear TMR2 just before I load a new duty cycle value, so rollover 
is impossible in the time before I force it to happen.

Thank you Olin for insisting that PICs are never broken.
Just the programmer.

Hope this helps someone else who messes with PWM registers in 
unconventional ways. ALWAYS look at endpoint conditions and whether they 
can happen unexpectedly.

Robert

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