Russell, Good catch on Figure 20. I missed that completely. I'll look into what kind of trace length and width will be required. I was trying to lay things out with short and wide supply traces - I guess that will change now. Thanks for the tip on measuring ESR. Rather neat. Regards, Gordon Williams ----- Original Message ----- From: "Russell McMahon" To: "Microcontroller discussion list - Public." Sent: Monday, March 29, 2010 6:01 PM Subject: Re: LDO regulator > c> I don't see anything in the Max. Ratings section that would cover "back > > driving" like this. Would this typically be acceptable for this > > configuration. > > Fig 20 seems to cover your situation explicitly. > I read that as meaning that with the regulator set to a nominal 3.8V > output and with Vin = 0 then applying a voltage to the output produces > a linear resistive response of about 80 k. > E&OE YMMV. > > Vin = 0 MAY assume hard grounding of Vin, as happens when there is a > solid resistive load sharing the input voltage at Vin and power is > removed. It seems likely that having Vin floating is less damaging > again but again YMMV. > > Classic ye older regulator problems happened when Vin was crow barred > and Vout cap discharged through regulator. Death happened. Solution > was a back diode across regulator. It seems unlikely to be needed, > given Fig 20, but adding a reverse Schottky diode across LDO may add > safety. And, if load drops to near zero power may add problems at very > high temperatures as Schottky leakage exponentially rises - BUT also > not usually a problem. > > So. Common sense and data sheet seem to suggest it's OK. I don't > recall a fig 20 type diagram in other data sheets - well done ST - > assuming I'm interpreting it correctly. > > > The output cap ESR stability range is given in Fig. 21. The allowable range > > is roughly 0.05 to 2 Ohms for a 2uF output cap. The caps that I'm going to > > use are ceramic SMD 805 (no name, Chinese). Will the ceramic cap meet the > > 0.05 Ohms ESR requirement typically? From what I've been able to see is > > that ceramic caps are < 0.015 ESR therefore I would be below the > > requirement. Suggestions? > > Re cap ESR - I'd agree with you that it seems marginal. > However, 0.1 ohm track etc resistance probably not too hard to dind > with suboptimal placement - shame when components get "too good" for a > circuit :-). > > Cap ESr will vary with brand and more. > > If this is one off or small quantity you can measure actual ESR with a > VERY simple tester. > Apply a square wave via a small resistor to CAP. At square wave > transition the voltage will step jump in magnitude and then ramp > exponentially as capacitor charges. The step jump is Vin x ESR/(ESR > + series_R) or rearranging > > ESR = Vstep x Rseries / (Vin - Vstep) > Oscilloscope allows actual Vin at series resistor and Vstep to be measured. > > Too small Rseries loads square wave muchly. > Too large Reseries reduces Vstep size muchly. > > > Russell McMahon > -- > http://www.piclist.com PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist