On 2010-02-19 21:28, Josh Koffman wrote: > Hi all. > > I've just come across a problem that I've never had happen before. > Likely that was due to luck. Now I'm not sure what the best way to > solve it is. > > At the start of my ISR, I save WREG, STATUS, and BSR (this is a > PIC18F) to temporary registers. How are these "temporary register" allocated ? Should be via UDATA_ACS, are thay ? > I then restore them on exit. I've been > tracking a bug that seems to be manifesting itself due to incorrect > bank selection. Here's why I think this is happening, look at the > addresses of the following registers: > > W_Temp 0x080 > PORTA 0xF80 > > The other registers have similar overlapping low byte addresses. > So...going into my ISR I might not be in the correct bank. Does not matter a bit, since the temp regs are in the access bank anyway. Or at least should be. > But if I > change the bank, I've upset the current state and things won't get > restored correctly. > > I'm not really sure what to do on this one. Simple. Just make sure your temp-regs are in the access bank ! -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist