Hi guys, Are there any PLL experts in the room? I'm hacking together a primitive VBI data extractor using a CPLD (or maybe an FPGA), some RAM, and a bit of analog support circuitry (LM1881 sync separator and some comparators/video opamps). It looks like getting the video signal, stripping the sync, and producing a "data only" signal will be fairly easy: - Take CVBS in - Use the BURST output from the LM1881 to drive a sample-and-hold circuit. This provides the BLACK level. - Use a BAT85 (or BAT54) and a capacitor as a peak detector to get the WHITE level. Buffer with an opamp. - Connect WHITE level to the top of a 1:1 resistive voltage divider. Do the same for BLACK level. This is the CLIPPING LEVEL REF. Buffer if you feel pessimistic. - Take the CVBS video, feed it to +ve input of a comparator. Feed the -ve input from CLIPPING LEVEL REF. The output of the comparator is the Teletext Data (TTX DATA). .. Now I need to extract the clock. To do this I was going to use a PLL (solely because I can't think of another way to do it that doesn't require a stupidly high frequency clock). The video line is 64us long, with a Teletext data rate of 6.9375Mbps. That means 0.144us (144ns) per bit. Each line consists of 360 bits, i.e. 45 8-bit bytes. The first two bytes are a clock run-in (101010... sequence), followed by a 1-byte framing code (11100100). Header data is sent as "dHdHdHdP" where d=data bits, H=Hamming ECC bits, P=parity bit. Page text data is sent as "dddddddP" (7 data bits, 1 parity bit). Parity is odd, thus the maximum (theoretical) number of zeroes in a run is 14 (per "Broadcast Engineers Reference Book" p.219). The full TV line is 64us, with ((1/6.9375e6)*360) = 51.89us of actual data. Frontporch, Hsync and Backporch add up to (1.65+4.7+5.7) = 12.05us gap between data bursts (with an uncertanty of about 60ns). What I need is something that can lock onto the clock run-in (16 bits * (1/6.9375e6) per bit = 2.3 us), hold the lock for the rest of the line (49.59us), and sync up just as quickly on the next VBI line (which may or may not be sync'd to the previous line). Basically, as soon as the next line appears, all bets are off. Now onto the questions... 1) How would I go about configuring a PLL to lock onto this? The HC4046 datasheet seems to assume you're locking two 50:50 signals against each other (translation: making a clock synthesizer). "Phase Locked Loops: Design, Simulation and Applications" pp.105- implies that an edge detector (four inverters and a XOR) is needed to get a lock, doesn't really explain why, then jumps straight into "delay modulation"... 2) Is there any way to configure the 4046's VCO to run off an external crystal, or would I have to build up an external VCXO for that? I was thinking Pierce oscillator + varactor diode, but those are a bit thin on the ground these days (seems the manufacturers don't make 'em any more, and the hams have bought up most of the stock). Not really what you want in a new design... 3) Say I wanted to sync the PLL up on the preamble (clock run-in), then leave it "free-running" at whatever frequency it was last running at / locked to. Would disconnecting the input to the loop filter in some way (say, two back-to-back small signal MOSFETs) be enough to do this, or can anyone suggest a better way that'll work at ~64us/line rates? If I disconnect F_in, I'm just going to get an output of Fvco_min (for PC2) or Fvco_mid (for the XOR PD). Disconnecting the loop filter sounds like it should work, but there's the impedance of the input circuitry to deal with (which AIUI is quite high, the HC4046 is CMOS). I'm sure this is simple to someone, but for some reason I can't get my head around the maths involved... Thanks, -- Phil. piclist@philpem.me.uk http://www.philpem.me.uk/ -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist