On Tue, 17 Nov 2009, Bob Blick wrote:

> I'm migrating an old project that used a 16F876A to a 16F886 and while
> checking the I2C part (yes, it stopped working) I notice what appears to
> be both a discrepancy and lack of information in the datasheets.

> Am I correct that in master mode, the I2C baud rate is based on 1/2 
> the crystal frequency divided by the bottom 7 bits of SSPADD?

Not as far as I can see.

> Is there a document that actually lists this without contradictions?

I can't see a contradiction in the data sheet.

Page 181 of the 16F88x data sheet says:

I2C Master mode, clock = FOSC / (4 * (SSPADD+1))

Page 195 says, "In I2C Master mode, the reload value for the BRG is
located in the lower 7 bits of the SSPADD register.  [...] The BRG
count is decremented twice per instruction cycle (TCY)."  Figure 13-12
shows that a BRG reload occurs every (SSPADD+1) counts and that it
toggles the state of SCL; i.e., the SCL frequency is half the BRG
reload frequency, and the BRG reload frequency is (Fosc / 2) / (SSPADD+1). 
This matches the equation on page 181.  I've not seen a PIC16 or PIC18
that doesn't use this same equation.

--
John W. Temples, III
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