On Fri, 2009-10-23 at 13:47 -0700, Barry Gershenfeld wrote:
> USB 3 operates at 5 gigabits/sec (like PCI-Express), uses separate transmit
> and receive differential pairs, (like PCI-E), data scrambling (like PCI-E),
> a link training phase (like PCI-E), and spread-spectrum clocking (like
> PCI-E)...One naturally wonders why we couldn't all just use External PCI-E,
> so I have to assume the advantage is not going to be found in the electrical
> specs.  

Complexity of end point is also a major factor.

A major BENEFIT of USB over Firewire when they were both new was
complexity of the end point. 

Firewire is very peer to peer in complexity, the host port is pretty
much the same amount of silicon and software as the thing being plugged
into it.

USB pushes much of the complexity on the host side, leaving cheaper and
simpler peripherals.

A PCIE endpoint is pretty complicated from a silicon perspective (I
know, I've debugged their inner workings a good bit). I can't say
exactly how much less complicated a USB3 endpoint is from hardware
perspective, but I'd imagine the designers used a similar methodology as
earlier USB designs when considering things.

Don't get me wrong, any piece of silicon running at those speeds isn't
"simple", it's a matter of being relatively more simple.

TTYL

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