On Thu, Oct 22, 2009 at 8:19 AM, Olin Lathrop w= rote: > Scott wrote: >> Currently I can send a Start Condition and load SSPBUF with the first >> byte to send, then I wait for the R_W bit to go low before writing to >> SSPBUF again. No interrupts are enabled, I2C is done via polling the >> SSPSTAT bits. =A0I'm looking at SDA and SCL on a 'scope. >> >> Problem: the I2C doesn't pump out the second byte. > > I'm not really following what exactly is happening, but polling the RW bit > is something you do in slave mode, not in master mode if I recall correct= ly. > In the past there have been problems with the IIC hardware, so I now often > just do the master in firmware where I can make sure everything is done > sequentially and avoid any race conditions. > According to the datasheet, in Master mode: R_W =3D 1 -- Transmit is in progress R_W =3D 0 -- Transmit is not in progress The datasheet is not clear at all about I2C Firmware Controlled Master mode vs. Master mode. It states "Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I2C bus may be taken when the P bit is set, or the bus is Idle, with both the S and P bits clear" and "In Firmware Controlled Master mode, user code conducts all I2C bus operations based on Start and Stop bit conditions." Could you please enlighten me on the differences, particularly how one goes about setting Start and Stop conditions as well as writing to SSPBUF. Thanks, Scott -- = http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist