Bypass caps also need to take into consideration of the switching frequenci= es of the devices. Xilinx has had some really good papers on this, targeti= ng the FPGA design of course, but this is a good starting point. Back in t= he day, sprinkling 0.1uF on each device was deemed sufficient and probably = is for most PIC based designs. http://ftp.cse.sc.edu/jdavis/csce613/Xilinx/Vertex-AppNotes&Sample%20Code/x= app158.pdf --- On Mon, 10/12/09, William "Chops" Westfield wrote: > From: William "Chops" Westfield > Subject: [EE] Bypass capacitor question > To: "Microcontroller discussion list - Public." > Date: Monday, October 12, 2009, 10:08 AM > Speaking of ceramic caps... > = > A 0.1uF cap has long been the standard for power supply > bypass=A0 = > capacitors of most ICs.=A0 Occasionally you'd see > smaller values=A0 = > (0.01uF) in higher frequency designs. > = > As I understand it, the idea was that smaller value caps > had "better"=A0 = > characteristics such a lead and internal inductance, ESR, > and so on.=A0=A0=A0 > While bigger caps had, well, more capacitance.=A0 0.1uF > was the "sweet=A0 = > spot" for most apps. > = > So, that was all about a generation ago.=A0 TTL and > ceramic disk caps.=A0=A0=A0 > Nowadays, I wonder if these rules of thumb are > obsolete.=A0 It's hard=A0 = > for me to imagine that a 0.1uF 0805 SMT ceramic cap has > much different=A0 = > non-capacitance features from a 10uF 0805 SMT ceramic cap > (different=A0 = > dielectric, different max voltage, yeah, but those are less > relevant=A0 = > to bypass, right?)=A0 The situation is similar for > leaded multilayer=A0 = > ceramic caps (SMT cap with leads, pretty much, eh?) > = > So is there some new reason for carefully picking bypass > cap values=A0 = > (modern CPUs and certain chips get very picky, but is that > more of=A0 = > "we're sure that this works" rather than "this is actually > what is=A0 = > required"?)=A0 Is more capacitance better, within a > certain smt cap=A0 = > size, as long as rated voltage stays high enough?=A0 Are > the exotic=A0 = > dielectrics that permit 100uF ceramic caps (ok, bigger than > 0805!)=A0 = > subject to odd physics that makes them poor bypass > caps?=A0 What ARE the=A0 = > new rules, or new concerns, now that lead-length and long > spools of=A0 = > foil are no longer players? > = > Thanks > Bill W > = > -- = > http://www.piclist.com PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > = = -- = http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist