Hi Bill,

I cannot give you a complete answer but I do have a few items that I
learned recently:

1) The "miracle" multi-layer ceramic chip capacitors which have >1uF
capacitance do have some strange behavior. First of all, their
capacitance is given for 0V DC bias. It is often significantly lower
as you approach their max rated voltage. For example, I tested some
2.2uF, 100V, 1210 and 1810 size MLCC caps from several manufacturers
(Taiyo Yuden, Murata, Kemet). All of them showed a capacitance of >2uF
at 0V bias, but at 50V, some were as low as 1.5uF. They also are
significantly piezoelectric. If you put an audio frequency current
through them, you can hear them like little speakers. Also, the
capacitance change due to DC bias is somewhat time dependent. For
example, if you take one of these caps and measure its capacitance at
0V, you may get 2uF. Then, you apply 50V, and get 1uF. Now, you
suddenly discharge the capacitor to 0V and measure its capacitance
again. It might be 1.5uF and then slowly (over the course of minutes)
drift back down to its original 2uF capacitance.

2) I think that it is still true that, for a fixed case size, there
will be a range of capacitance which has the lowest ESR and ESL
(effective series resistance and inductance). For one thing, the
higher the capacitance per volume, it is likely that they have to
sacrifice metalization thickness and have a longer average path from
end contact to all parts of the plates.

Sean

On Mon, Oct 12, 2009 at 1:08 PM, William "Chops" Westfield
<westfw@mac.com> wrote:
> Speaking of ceramic caps...
>
> A 0.1uF cap has long been the standard for power supply bypass
> capacitors of most ICs. =A0Occasionally you'd see smaller values
> (0.01uF) in higher frequency designs.
>
> As I understand it, the idea was that smaller value caps had "better"
> characteristics such a lead and internal inductance, ESR, and so on.
> While bigger caps had, well, more capacitance. =A00.1uF was the "sweet
> spot" for most apps.
>
> So, that was all about a generation ago. =A0TTL and ceramic disk caps.
> Nowadays, I wonder if these rules of thumb are obsolete. =A0It's hard
> for me to imagine that a 0.1uF 0805 SMT ceramic cap has much different
> non-capacitance features from a 10uF 0805 SMT ceramic cap (different
> dielectric, different max voltage, yeah, but those are less relevant
> to bypass, right?) =A0The situation is similar for leaded multilayer
> ceramic caps (SMT cap with leads, pretty much, eh?)
>
> So is there some new reason for carefully picking bypass cap values
> (modern CPUs and certain chips get very picky, but is that more of
> "we're sure that this works" rather than "this is actually what is
> required"?) =A0Is more capacitance better, within a certain smt cap
> size, as long as rated voltage stays high enough? =A0Are the exotic
> dielectrics that permit 100uF ceramic caps (ok, bigger than 0805!)
> subject to odd physics that makes them poor bypass caps? =A0What ARE the
> new rules, or new concerns, now that lead-length and long spools of
> foil are no longer players?
>
> Thanks
> Bill W
>
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