>> If hysteresis is unspecified or even is absent, - this won't
>> be a problem for SDO or SS lines, but for slowly rising/falling
>> SCK (due to divider's resistors) this may cause "level
>> bouncing" near the point when logical "0" level starts to
>> be interpreted as high.
>
> Years ago I had problems with a rather long SPI bus that
> was driving a PLD. The PLD was real fast and would detect
> ringing on the SPI clock line causing the SPI data to
> occasionally be off by a bit.
>
> On using voltage dividers as level translators (5V to 3.3V),
> the use of low resistor values is an attempt to present a
> low Thevenin resistance to the 3.3V side so capacitive
> loading does not slow the edge too much. An idea I
> mentioned before, though, would be to put a small capacitor
> across the top resistor so we have a resistive divider in
> parallel with a capacitive divider. This is just like scope
> probe compensation and should eliminate the slow edge
> due to voltage divider resistance.

Yes, I meant "ringing on the SPI clock line causing the SPI data to
occasionally be off by a bit."

In my opinion a small capacitor across the top resistor will introduce
new problems, and won't solve the main problem: the voltage is
constructed on the sender side, not on recipient's side.

Why not just drain current to ground on the sender side by open
collector or open drain. Then on recipient's side the current would
create a voltage on a resistor connected to recipient's Vdd.

Open collector or open drain can only drain current, not inject it to
the resistor/input capacitance. Thus you are guaranteed the voltage on
the input (relative to Vdd)  would only increase in abs value
regardless of voltage disturbances along the bus. There will be no
"ringing" on the input. Just sense the input signal relative to
recipient's Vdd.


> However, as the parts count goes up, I'm real tempted to just buy a level
> translator chip. Especially if there are several lines to be translated.

They may not work well for a long bus as they only translate voltage,
they don't "drain "current.
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