> If hysteresis is unspecified or even is absent, - this won't be a
> problem for SDO or SS lines, but for slowly rising/falling SCK (due to
> divider's resistors) this may cause "level bouncing" near the point
> when logical "0" level starts to be interpreted as high.

Years ago I had problems with a rather long SPI bus that was driving a
PLD. The PLD was real fast and would detect ringing on the SPI clock line
causing the SPI data to occasionally be off by a bit.

On using voltage dividers as level translators (5V to 3.3V), the use of
low resistor values is an attempt to present a low Thevenin resistance to
the 3.3V side so capacitive loading does not slow the edge too much. An
idea I mentioned before, though, would be to put a small capacitor across
the top resistor so we have a resistive divider in parallel with a
capacitive divider. This is just like scope probe compensation and should
eliminate the slow edge due to voltage divider resistance.

However, as the parts count goes up, I'm real tempted to just buy a level
translator chip. Especially if there are several lines to be translated.

Harold




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