Michael Rigby-Jones wrote:
> Are you genuinely failing to understand what people are trying to
> explain, or are you now trolling?
>
> 1) With a 5v signal, and a potential divider of 2k and 3k, the final
> voltage will be 5 * 3/(2+3) =3D 3v. =A0The source impedance will be 3k||2=
k =3D
> 1.2k. =A0The 10%-90% voltages will be 0.3v-2.7v.
>
> 2) With a 5v signal, and a potential divider of 2k and 2.95k, the final
> voltage will be 5 * 2.95/(2+2.95) =3D 2.98v. =A0The source impedance will=
 be
> 2.95k||2k =3D 1.19k. =A0The 10%-90% voltages will be 0.298v-2.682v
>
> Assuming both circuits are driving the same capacitive load the rise and
> fall times will be slightly lower (faster) in the second case due to the
> lower source impedance, but the voltage swing will be slightly lower as
> well. =A0Do you now understand? =A0If not then I can recommend 'The Art of
> Electronics' to gain a basic understanding of these principals.

First, we are talking only about rising voltage on a capacitor, we ARE
NOT talking about how the capacitor will be DISCHARGED through the
resistors, please, re-read my previous post.

Second, let's refresh the scheme: we have a capacitor connected to
ground by one leg and through its other leg and resistor R1 getting
connected to DC source. Also there is a resistor R2 connected to the
capacitor IN PARALLEL. That second resistor _ALWAYS DISCHARGES the
capacitor, that is, tries to diminish the voltage on the capacitor,
you may call that resistor - leakage resistance.

How, the hell on the earth, lower R2 value, that is increase in
current leakage to ground from the capacitor would help the DC source
to charge the capacitor faster through the same constant resistor R1?
Lower R2 would mean lower impedance according to you.

-- =

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