> -----Original Message-----
> From: piclist-bounces@mit.edu [mailto:piclist-bounces@mit.edu] On
Behalf
> Of Marechiare
> Sent: 03 October 2009 17:26
> To: Microcontroller discussion list - Public.
> Subject: Re: [PIC] PIC SPI level conversion
> 
> 
> Moreover this asymmetrical rise/fall time DOES work for "FET +
> resistor" approach.  It's much better to synch to sharp falling edge
> as in the "FET + resistor" approach, than to fuzzy many factors
> dependent any edge as in "Voltage Divider" case. If I am not mistaken
> the phase of SCK could be programmatically adjusted for newer PICs.
> Set the edge sharp, and adjust the SCK phase properly.

The phase of the data and clock can indeed be adjusted programmatically,
but the requirements are set ONLY by the devices you are driving, not by
the solution which happens to give you the best rising and falling
edges.  If you set the incorrect phase then SPI devices will either not
work correctly or at all, or worse will work intermittently.

You seem to have this idea that the faster the edge the better, this is
far from the truth in the real word.  Fast edges can cause many problems
in circuits, so it's a good idea to have edges that are fast enough to
provide enough timing margin but not significantly faster.  If you need
faster edges than the purely resistive divider can achieve for a given
capacitive load, it's a simple matter to use a capacitor across the
upper resistor to provide a compensated divider.

As others have said, the rise and fall times of an edge are always
relative to the final value of the signal; typically you would quote the
10%-90% or 20%-80% time (and tell people which one you are using).  You
can't possibly use a fixed voltage as a reference; if you changed the
potential divider so the final voltage was less than 2.9v, this would
give a rise time of infinity by your definition. 

Regards

Mike

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