> when we decrease divider's bottom resistor 3.9K to 3.85K,
> the time to rise the signal on the capacitor from 0V to 4.9V
> will decrease as per your statement that - the lower impedance -
> the higher speed of signal rising on that capacitor.

Siorry, a typo, should be "from 0V to 2.9V" not "from 0V to 4.9V"

Thus

So, may I conclude that you insist that for your circuit

"perfect 0 to 5V square wave followed by the 2K,3.9K ohm
divider, driving some capacitive load connected to ground"

when we decrease divider's bottom resistor 3.9K to 3.85K, the time to
rise the signal on the capacitor from 0V to 2.9V will decrease as per
your statement that - the lower impedance - the higher speed of signal
rising on that capacitor.
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