>>> My standard answer is 2K ohms in series
>>> followed by 3.9K ohms to ground for 5.0V to 3.3V
>>
>> Do I understand it correctly:
>> - The output connects to 2K resistor;
>> - The other leg of that 2K resistor is connected to 3.9K resistor;
>> - The other leg of that 3.9K resistor is connected to ground;
>> - The input is connected in between 2K and 3.9K resistors;
>
> Yes.
>
>> The threshold voltage 2.6V is quite close to that 3.1V and the
>> approximation curve is quite smooth, so the input signal would reach
>> 2.6V later than it would reach when there is no that 3.9K resistor.
>
> I can make a much faster circuit too if it doesn't have to work right. =
=A0Your
> hypothetical circuit is pointless since it's violating the maximum output
> voltage spec.
>
> Think of it this way: =A0Compare two circuits, one is a perfect 0 to 5V s=
quare
> wave followed by the 2K,3.9K ohm divider. =A0The other is a perfect 3.3V
> square wave followed just by 2K ohms in series. =A0Now assume each is dri=
ving
> the same capacitive load. =A0Which one will have faster rise and fall tim=
es?

Well, if you don't want talking about "hypothetical circuit", let us
not. Let's compare the OP asked about:

I did that in one of my previous posts:

***
> Voltages are 5V and 3V, those OP requested.
>
> For Voltage Divider:
> Voltage divider is 2K + 3K.
> Power consumption factor 5V * 5V / 5KOhm =3D 5mW
>
> For FET & Resistor
> Power consumption factor 5mW, thus resistor is
> 3V * 3V / 5mW =3D 1.8 KOhm
>
> That is, 2K + 3K Voltage Divider would consume the
> same power as FET + 1.8K resistor
>
> Let's compare their timings now:
>
> Yes, 5V / 2K =3D 0.0025 slope factor is better than
> 3V / 1.8K =3D 0.0017
>
> But, please, keep in mind that the above is true only for
> rising edge. For falling edge the divider works through
> the same 2K and the FET works directly through its
> aprox 1 Ohm Rds(On).
>
> Thus the sum of rising and falling transition times is
> considerably worse for the "Voltage Divider" case compared
> to the case of FET + resistor when both approaches are
> consuming the same power.
***

Do I need to repeat that

> the sum of rising and falling transition times is considerably
> worse for the "Voltage Divider" case compared to the case of FET +
> resistor when both approaches are consuming the same power.

-- =

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