>> Aha, I see, the problem is that I ommited the magic word "COULD". Ok,
>> if I had written " It COULD be much better to synch to sharp falling
>> edge" - would the rest hold true about FET + resistor to VERY PROBABLY
>> be better than the divider in many designs?
>
> That would very probably not be true, but it depends on your value of
> many. 1k out of 1M is still quite a lot, so it might qualify for your
> 'many'.
>

Ok if I removed VERY from my statement, would I qualify to avoid the
kind of crucifixion for propagating bad EE practicies?

> Think for instance about
> - inverting the signal

So, you think only 1k out of 1M designs do not care of it? Others
can't invert the bits programmatically (if needed).

> - slower rising edge
Rising edge for the voltage divider is faster sort of 30%, but falling
edge is slower much much more.
So, you think that for 999K of 1M designs these 30% are vital for the
rising. And much faster falling does not matter?

> - takes current from the lower voltage supply
> instead of taking it from the higher voltage supply
> (probably just as likely to be an advantage too, but
> still an argument against blanket-like statements)

The main advantage is that it references to the input's chip Vdd. The
gap for logic "1" input voltage is quite narrow. With the divider you
are risking to either overvoltage input or just not reach the logic
"1".

etc, etc
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