> I left out some steps in deriving the design equations and
> more steps at the end to keep this to one page, but it's
> just algebra.
>
> My conclusion is that the voltage divider has lower maximum
> power consumption unless Va >= 2*Vb.
>
> So, it's better for 5V->3.3V, equal for 5V->2.5V and worse
> for 5V->1.8V, all other things being equal.
>
> Similarly, it's easy to see that the max current drawn is
> always better with the voltage divider (they are only equal
> when Vb == 0).

Yeah, Algebra is The Argument. Let's check your math with just common
sense and some simple arithmetics (to SW: Ohms Law involved).

Voltages are 5V and 3V, those OP requested.

For Voltage Divider:
Voltage divider is 2K + 3K.
Power consumption factor 5V * 5V / 5KOhm = 5mW

For FET & Resistor
Power consumption factor 5mW, thus resistor is 3V * 3V / 5mW = 1.8 KOhm

That is, 2K + 3K Voltage Divider would consume the same power as FET +
1.8K resistor

Let's compare their timings now:

Yes, 5V / 2K = 0.0025 slope factor is better than 3V / 1.8K = 0.0017

But, please, keep in mind that the above is true only for rising edge.
For falling edge the divider works through the same 2K and the FET
works directly through its aprox 1 Ohm Rds(On).

Thus the sum of rising and falling transition times is considerably
worse for the "Voltage Divider" case compared to the case of FET +
resistor when both approaches are consuming the same power.

Moreover this asymmetrical rise/fall time DOES work for "FET +
resistor" approach.  It's much better to synch to sharp falling edge
as in the "FET + resistor" approach, than to fuzzy many factors
dependent any edge as in "Voltage Divider" case. If I am not mistaken
the phase of SCK could be programmatically adjusted for newer PICs.
Set the edge sharp, and adjust the SCK phase properly.
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