>  But forgive me, I don't understand your writing and thus can't discuss it.

It's just a fun mathematical exercise-- algebra, Ohm's law and Thevenin
equivalents, and time constants.

Hopefully this will help--

http://speff.com/divider_pullup.jpg

I left out some steps in deriving the design equations and more steps at
the end to keep this to one page, but it's just algebra.

My conclusion is that the voltage divider has lower maximum power
consumption unless Va >= 2*Vb.

So, it's better for 5V->3.3V, equal for 5V->2.5V and worse for 5V->1.8V,
all other things being equal.

Similarly, it's easy to see that the max current drawn is always better
with the voltage divider (they are only equal when Vb == 0).

One uses power when low and the other when high, so the comparisons are
a bit flawed in real situations such as SPI!

Best regards,

Spehro Pefhany --"it's the network..."            "The Journey is the reward"
speff@interlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com



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