At 12:18 PM 02/10/2009, you wrote:

>Energy consumption, not current consumption may be important.  With
>3.3V you can afford more current than with 5V for the same energy
>spent. And you can afford even more current to inputs since when
>charging inputs a lot of current is getting wasted through the bottom
>resistor of the divider. So, for the same energy consumption the speed
>of the rising edges may not necessarily be lower.

The open drain/pullup method gives asymmetrical rise/fall time. Fall
time is relatively low (Rds(on) * C) and rise time is  proportional to
R*C. The divider method gives (very close to) equally slowed rise and fall
times assuming a CMOS output and reasonable resistor values. Ignoring that..

For a 1:2 ratio of divider resistances (divider ratio 2/3) and
5V/3.3V supplies, and equal RC product, we get a current ratio of about
3:1 in favor of the divider, and a power consumption ratio of about 2:1,
also in favor of the divider.

You don't see a break-even in terms of power until you reach a 2:1
ratio in supply voltages (eg. translating from 5.0V to 2.5V).

Of course neither approaches the low power consumption of some translator
chips-- in the uA range under static conditions.

Best regards,

Spehro Pefhany --"it's the network..."            "The Journey is the reward"
speff@interlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com



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