> > mainline code must complete, ISR must complete
> 
> OK, got it now. So if watchcat is not inverted twice to its original
> value then a WDT timeout results. That could cover any number
> of routines, perhaps by addition to watchcat, to a test value

To be pedantic in my example if watchcat is not inverted once then a WDT occurs. 
The second inversion is only after a successful WDT reset, so the cycle can 
continue. Yes, you could do some quite clever things with multiple routines each 
adding a unique value to a checksum. Working with a SiLabs 8051 at present - to 
disable the WDT you write 0xDEAD to it!

-- 
Brent Brown, Electronic Design Solutions
16 English Street, St Andrews,
Hamilton 3200, New Zealand
Ph: +64 7 849 0069
Fax: +64 7 849 0071
Cell: +64 27 433 4069
eMail:  brent.brown@clear.net.nz


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