> Hi again Harold,
>
> You are welcome. Which DDS chip are you using?
>
> Yes, without low-pass filtering, the dominant spurious outputs will be
> at the clock frequency plus and minus the desired output frequency.
> Once you filter those out, however, your signal will not be completely
> clean. You will still have DAC quantization noise and phase
> accumulator truncation noise. These should not be visible on most
> scopes, though, and you will probably get close enough for your
> purposes.
>
> You will need a good low-pass filter for this - not a simple RC one. I
> would recommend a 5th order or greater Chebychev or Elliptical LPF,
> designed using a table or one of the online free design tools. Your
> desired output frequency is more than 1/10th of the master clock, so
> you don't have much frequency "room" for filtering.
>
> The programmable oscillator blocks are notorious for high spurious
> output content. However, this is not because of the type of VCO they
> use - it is rather because of their very generic and simple PLL
> divider design. Even if you have a VCO with very high phase noise, the
> PLL will clean that up to a large degree. Usually the ultimate
> determinant of the phase noise of a PLL output is the multiplication
> (or division) factor (Fout/Fref) times the phase noise of the
> reference.
>
> Sean

Thanks! I'm using the AD9833 eval board. I'm guessing a multi-stage LC LPF
would be best here instead of doing something active, right?

Harold


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