Hi again Harold, You are welcome. Which DDS chip are you using? Yes, without low-pass filtering, the dominant spurious outputs will be at the clock frequency plus and minus the desired output frequency. Once you filter those out, however, your signal will not be completely clean. You will still have DAC quantization noise and phase accumulator truncation noise. These should not be visible on most scopes, though, and you will probably get close enough for your purposes. You will need a good low-pass filter for this - not a simple RC one. I would recommend a 5th order or greater Chebychev or Elliptical LPF, designed using a table or one of the online free design tools. Your desired output frequency is more than 1/10th of the master clock, so you don't have much frequency "room" for filtering. The programmable oscillator blocks are notorious for high spurious output content. However, this is not because of the type of VCO they use - it is rather because of their very generic and simple PLL divider design. Even if you have a VCO with very high phase noise, the PLL will clean that up to a large degree. Usually the ultimate determinant of the phase noise of a PLL output is the multiplication (or division) factor (Fout/Fref) times the phase noise of the reference. Sean On Wed, Aug 19, 2009 at 11:03 AM, Harold Hallikainen wrote: > Thank you for the EXCELLENT response! From a brief reading of the > resources you posted plus a few more I found at Analog Devices, it appears > the spurious output is at the master clock frequency plus and minus the > final output frequency. If the final output frequency is considerably > below the master clock, it seems that it should be fairly easy to filter > it out. I'm using an AD eval board with a 25MHz master clock and output > frequencies of 3.45MHz and below. I'll go ahead and add an LPF to the sine > wave output, then run it in to a comparator. Maybe I can just use a > Schmitt trigger (like 74HC14) instead of a comparator to make it easier. > This is a local oscillator for an FM receiver that receives 2.3MHz and > 2.8MHz. The IF is 650kHz. I decided to use a DDS instead of a PLL > synthesizer (such as the programmable crystal oscillator modules) thinking > that the PLLs are using RC oscillators which have a fair amount of FM > noise. > > Again, THANKS for the response! > > Harold > > > > -- > FCC Rules Updated Daily at http://www.hallikainen.com - Advertising > opportunities available! > -- > http://www.piclist.com PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist