On Aug 18, 2009, at 5:22 AM, Olin Lathrop wrote: >> Essentially there is a relatively long idle period, followed by >> over 70 sequential data bits which are around 400ms long each, and >> at approx 1% timing error from the sender. > > Obviously this can't work. I agree with Olin. This is where schemes other than NRZ come in (even just stop and start bits in async serial), and why they're needed... BillW -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist