Hi John,

Do you have a linker script to show us? Maybe there is some special section
defined on that memory region already? I mean the debugger gets confused as
you are using a normal (aka non-protected) udata but forcing it to be on a
specific location?

Tamas



On Wed, Jul 22, 2009 at 11:23 AM, JohnSanderson <john@jscontrols.co.za>wrote:

> Hello Olin & Picers,
>
>
> ----- Original Message -----
> From: "Olin Lathrop" <olin_piclist@embedinc.com>
> To: "Microcontroller discussion list - Public." <piclist@mit.edu>
> Sent: Tuesday, July 21, 2009 11:40 PM
> Subject: Re: [PIC] IDE Watch window
>
>
> > JohnSanderson wrote:
> >>  UDATA_ACS  for shared variables
> >>  UDATA  0x0100 for the maths source
> >>  UDATA  0x0200 for the main source
> >
> > Making sections absolute when they don't really need to be is a bad idea.
> > Only one module in the whole project can use UDATA h'100'.  If another
> > module tries to do this too, the two sections will collide and you will
> > get
> > the "can not fit section" linker error.  You would also be hard coding
> > where
> > the banked memory in bank 0 starts, which varies between parts.  Yucc.
> >
>
> ..
>    Absolute coding, bad idea. Sounds fair, I just did it out of a desire to
>    define everything.    Not a necessity.
>
>    Anyway, there were no linker errors and the .map file showed that all
>    the GPR data had a place of its own.
>
>    The question was posed to seek reason/s  why the watch window
>    would not update and display GPRs for data bank2 and higher.
>    Currently I'm running with all the data fitting into banks0 & 1 so
>    I'm able to watch everything I need. Still no further to finding out why
>    I can't see into banks2+.
>
>    I've tested this with other legacy code that definitely works properly,
> so
>    it has to be the case that Real-Ice/IDE is failing to display values
> that really
>    do exist.
>
> ..
>
>
> > Why not just do it right?  If you want to force particular banks at
> > assembly
> > time, create named sections in the linker for each bank.  Then reference
> > these named sections in the source code:
> >
> > bank1  udata
> >
> > Any number of modules can do this, and there won't be a error unless the
> > total memory requested for bank 1 exceeds the size of bank 1.
> >
> > See my linker files where I set up named sections for exactly this
> > purpose.
> >
> >> For debugging I want to watch what's happening with a whole
> >> selection of fregs.
> >
> > What's a "freg"?
> >
>
> ..
>    GPRs
> ..
>
>
>
>            best regards,   John
>
>
> eMail from the desk of John Sanderson.
> JS Controls cc. Manufacturer and purveyor of Force testing
> apparatus.
> john@jscontrols.co.za
> www.jscontrols.co.za
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