Heinz Czychun wrote:

> I think I understand it now. My confusion was I didn't understand the  
> changing significance of the interrupt enable bits (eg T0IE) and  
> interrupt flag bits (eg TOIF). Their significance changes depending  
> on whether execution is in the main code, or in the interrupt service  
> routine.

I do not think so. For one thing, the processor itself can not
tell if it is in the "main" code or in the "ISR". It's just a
logical way of splitting the code. The "interrupt" itself is
more or less a simple GOTO to h'0004' with a few additional
bits set/cleared on the way. There is no way for either
the processor or your code to know/see that it is currently
inside the part of your code that you has called "the ISR"...

So, no, nothing in the processor changes in the way it works
dependig in what part of the code is executing.

> In the main code the interrupt enable bits are significant in that  
> they will prevent a peripheral from generating an interrupt. So the  
> interrupt flag bits can safely be ignored.

Yes.

> Once an interrupt (any interrupt) forces execution of the interrupt  
> service routine the interrupt enable bits become useful flags to tell  
> which peripheral's service request should be honoured.

Correct.

> But now the  
> interrupt flag bits (all that are set) become significant and cannot  
> be ignored.

If the xxIE bit is cleared, they can still be ignored.

> Whether the peripheral's interrupt enable bit is set or  
> not it's interrupt flag bit must be cleared or the processor will be  
> hung repeatedly reentering the interrupt service routine.

No, a set xxIF bit will not reenter the ISR if the xxIE bit is cleared.
Clearing a xxIF bit that you are not using is a waste of time.

> 
> That's the way I see what the manual is trying to explanation. Does  
> that sound right?
> 
> In this particular instance it is prohibitively difficult to stop  
> TMR0, and so I have to live with adding code that when it reads T0IF  
> set it clears it. I can safely ignore the T0IE bit because I know I  
> don't want the PIC to take action on it's rollover.

Simply clear T0IE and TMR0 should/will not generate any interrupt.

I think that you have to come up with a simple test-case that shows
what you think you are seeing.

Jan-Erik.
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