> Hi Jinx,
> =

> On 12-Jul-09, at 12:50 AM, Jinx wrote:
> =

> =

>      I disagree here they, the IFs, are very significant because you  =

> won't get out of the isr without clearing them.
> =

>      I see it as a dyke or dam. All is ok as long as all the water is  =

> kept out, no interrupts are allowed to happen. But once that first  =

> crack happens, an interrupt occurs, all the set IFs are suddenly seen  =

> by the cpu and need to be cleared before it can get back to the main  =

> code again. And your code has to tell it to do this. That's how  =

> interprete all the warnings in the manual about TMR0 settings its  =

> TOIF regardless of the TOIE, and that this must be cleared in 'your'  =

> software.
> =

>      I think that's why uChip has added an on bit to most (all?)  =

> peripherals, so they never can set their IFs when off, so don't need  =

> to be dealt with in the isr.  Timer0 being a legacy sort of  =

> peripheral (the first one?) doesn't have such a nicety.
> =

> =


This is not in accordance with figure 9-10 in the datasheet for the 12f629/=
675. =

When the IE bit is not set, the IF bit by itself can not cause the executio=
n of =

the ISR (either once or reentering it).

/Ruben
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=3D=3D=3D=3D=3D
Ruben J=F6nsson
AB Liros Electronic
Box 9124, 200 39 Malm=F6, Sweden
TEL INT +46 40142078
FAX INT +46 40947388
ruben@pp.sbbs.se
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
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-- =

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