Hi,
       In summary what I now think is correct:

1)  What I am seeing is normal behaviour.

2)  T0IF gets set every time Timer 0 rolls over

3)  2 above is only an issue if another peripheral causes an  
interrupt, then T0IF must be explicitly dealt with. Since Timer 0 is  
not easily turned off.

4)  I can only stop Timer 0 by:
  a) putting the chip to sleep
not very practical since the chip can't do much while asleep, and  
Timer 0 will start running again when the chip awakens.
  b) setting it as a counter and not using the input pin
  b1) setting it to an analogue input should work (input reads as zero)
Not practical on the 12F675 as it's AN2 and am not sure if AN2 can be  
an analogue input while AN0 & AN1 are Digital???
  b2) not sure if setting it to an output would also work??? Would  
the counter still register output transitions?

5)  So I'm left with dealing with the T0IF bit, when in the interrupt  
service routine.

I must say I was initially confused by the mention of T0IE, by Tamas,  
Jan-Erik, and Olin perhaps others. After all, hadn't I cleared this  
bit in the beginning, and so shouldn't this be a set (clear, in this  
instance) and forget item, right?

I think I understand it now. My confusion was I didn't understand the  
changing significance of the interrupt enable bits (eg T0IE) and  
interrupt flag bits (eg TOIF). Their significance changes depending  
on whether execution is in the main code, or in the interrupt service  
routine.

In the main code the interrupt enable bits are significant in that  
they will prevent a peripheral from generating an interrupt. So the  
interrupt flag bits can safely be ignored.

Once an interrupt (any interrupt) forces execution of the interrupt  
service routine the interrupt enable bits become useful flags to tell  
which peripheral's service request should be honoured. But now the  
interrupt flag bits (all that are set) become significant and cannot  
be ignored. Whether the peripheral's interrupt enable bit is set or  
not it's interrupt flag bit must be cleared or the processor will be  
hung repeatedly reentering the interrupt service routine.

That's the way I see what the manual is trying to explanation. Does  
that sound right?

In this particular instance it is prohibitively difficult to stop  
TMR0, and so I have to live with adding code that when it reads T0IF  
set it clears it. I can safely ignore the T0IE bit because I know I  
don't want the PIC to take action on it's rollover.


Thanks again for all your help,
Regards,
Heinz



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