Nathan House wrote:
> If I use the equation provided in the family reference manual to
> calculate ADCS, using 400ns as the Tad value (400ns is my instruction
> cycle time, Tcy),

Strange choice of PIC if you're only running it at 400nS instruction period.

> then the answer is "1." If Vincent Prats is
> correct, in that the smallest conversion time achievable is
> desirable, then my ADCS value should be satisfactory. But to my
> confusion, the manual shows an example where the Tad time is
> significantly longer then both the Tcy shown and the minimum Tad
> (83.33ns) time. Why would they do this?

First, the example may not be correct.  There are a lot of bad examples out
there.  Unfortunately the bozos that just took a whole week to blink a LED
and think they deserve a Nobel prize for it are more likely to post examples
of their bugware than those that write the code correctly in 5 minutes and
go on with things because it's not a big deal.  Some Microchip examples are
occasionally less than ideal, or at least not stellar examples of
programming discipline.

Second, what's the problem?  As long as the minimum and maximum Tad times
listed in the datasheet are adhered to, it's fine.  Someone at Microchip sat
down and figured out over what range the A/D lives up to its specs.  They
understand the tradeoffs more than we can.  You should generally just take
their word for it.

I can make a reasonable guess that at the low end of Tad the issue is
settling time of the comparator and other circuitry to decide the next bit.
At the high end it's probably the sample and hold drifting.  Any value in
between is good enough.


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