I apologize if I am getting on people's nerves with my perseverance on this
matter.

The 30F FRM says "The A/D converter requires one A/D clock cycle (TAD)
to..." Since I am using the system clock for the A/D module, does it make
sense to say that the time for one A/D clock cycle should equal the system
clock instruction cycle time?

If I use the equation provided in the family reference manual to calculate
ADCS, using 400ns as the Tad value (400ns is my instruction cycle time,
Tcy), then the answer is "1." If Vincent Prats is correct, in that the
smallest conversion time achievable is desirable, then my ADCS value should
be satisfactory. But to my confusion, the manual shows an example where the
Tad time is significantly longer then both the Tcy shown and the minimum Tad
(83.33ns) time. Why would they do this? Either my understanding of this
matter is wrong, or the example given is not as efficient as it could be.
Which is it?

[image: http://roboticsguy.com/images/misc/example_21.png]
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