Looks like old 2-level stack PIC12Cxxx to me, except it has flash data memory... --Bob On 7/8/09, Jan-Erik Soderholm wrote: > Alan B. Pearce wrote: >> datasheet at http://ww1.microchip.com/downloads/en/DeviceDoc/41338B.pdf >> >> 14 pin package. >> >> seems to be a RISC architecture - says it has a 'highly symmetrical >> instruction set', but no instruction set listed in data sheet. >> >> claims to have a C compiler available. >> >> Appears to have a 2 clock time instruction cycle with pipeline, instead of >> >> the 4 clock time instruction cycle of the base and midrange PIC devices. > > Not according to the linked datasheet. See fig 2-2 on p.10. > > It also says "All instructions are single cycle (200 ?s) > except for program branches, which take two cycles" > > I guess that 200 us ahould be 200 ns, and that is 5 MIPS witch > match a 4 phase cycle @ 20 MHz. > > It looks very similiar to the (old) base-line arch... > > Jan-Erik. > >> >> 20MHz max clock speed. >> > -- > http://www.piclist.com PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist