Rob Hamerling escreveu:
> Jan-Erik Soderholm wrote:
>
>   =

>>>>> It's the overlap of instruction fetching and execution which =

>>>>> *effectively* doubles the speed (compared to non-overlapping).
>>>>> See Exampe 2-1 on page 10
>>>>>           =

>>> Jan-Erik Soderholm wrote:
>>>       =

>>>> Douples compared to what ?
>>>>         =

>>> As I said: 'compared to non-overlapping'. Fetch/execution overlapping =

>>> seems to be standard in the baseline, unlike in the midrange.
>>>
>>> Regards, Rob.
>>>       =

>> I compared the new (?) MCV14A, the PIC10-series and the PIC16F628A
>> datasheets. They all have the same timing diagrams. The next fetch
>> is done while the former instuction executes in all three cases.
>>
>> Nothing "doubles".
>>     =

>
> Indeed, I had interpreted the figures wrongly! Sorry!
>
> Regards, Rob.
>   =


It appears that they stripped some bits off the core. The data address
range is just 128 bytes, perhaps the architecture doesn't have provision
for more. The program address bus may have been reduced also, to allow
just the 1K instructions.

This way they could save silicon area and make the chip cheaper.

Regards,

Isaac


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