Rob Hamerling wrote:
> 
> 
> 
> 
>>> Appears to have a 2 clock time instruction cycle with pipeline, instead of 
>>> the 4 clock time instruction cycle of the base and midrange PIC devices.
> Jan-Erik Soderholm wrote:
>> Not according to the linked datasheet. See fig 2-2 on p.10.
> 
>> It also says "All instructions are single cycle (200 ?s)
>> except for program branches, which take two cycles"
>>
>> I guess that 200 us ahould be 200 ns, and that is 5 MIPS witch
>> match a 4 phase cycle @ 20 MHz.
>>
> 
> It's the overlap of instruction fetching and execution which 
> *effectively* doubles the speed (compared to non-overlapping).
> See Exampe 2-1 on page 10

Douples compared to what ?


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