solarwind wrote:
> Section 2.1 of the dsPIC3FJ128GP802 shows a schematic of a minimal set
> of connections. For your viewing convenience, I have provided a link
> to the picture below:
>
> http://img150.imageshack.us/img150/5641/mincon.png
>
> 1. There is a 10 ohm resistor from AVDD to VDD. What is the idea behind this?
>   
Most likely to act in combination with the decoupling capacitor as a 
power supply filter for the analog supply. It can probablly be replaced 
with a wire if you aren't too concerned about ADC accuracy.

> 2. Could someone please explain what the circuitry near the MCLR pin
> is doing? Is it just a pullup on the MCLR with a decoupling cap? Or is
> there something else going on?
>   
It looks to me like a circuit designed to delay the rise of MCLR to hold 
the chip in reset while the power supply comes up and stabalises. Note 
that on the other side of that page they reccomend that you make the 
capacitor disconnectable and disconnect it for programming/debug purposes.

> 3. The dsPIC has an internal voltage regulator that regulates voltage
> to its core (I believe). What kind of regulator is it? (ex. linear,
> charge pump based, so on)
>   
I can't seem to find a reference in the datasheet but given that the 
only external component is a capacitor on it's output it is almost 
certainly a linear regulator.
> 4. I'm guessing that the decoupling caps act as mufflers for
> noise/spikes/dips and compensate for abrupt voltage changes. 
Their main purpose is to stop current spikes (which are a fact of life 
with cmos logic) turning into voltage spikes/dips
> In that
> case, I can see why they are placed in (parallel?) with the power
> lines. However, there is a cap placed in series with the VCAP/VDDCORE
> line. How does this cap behave? What does it do?
>   
It is in paralell with the regulator output. The regulator is connected 
internally to the core but you have to provide a decoupling capacitor to 
ground externally because large capacitors are very difficult/expensive 
to integrate in an IC.


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