Hi,

Thanks for these explanations. 


as2 wrote:
> 
> The work around is to read the port again after clearing the interrupt
> flag 
> and use the state from that read. Occasionally although you have read 
> the most recent pin state the change interrupt flag will be set again and 
> you will immediately take another interrupt where there was apparently no
> change. 
> 

I see. But in all cases I had already to determine witch edge so the logic
is
already present; there will be a small interrupt treatment for nothing, so
it 
should be OK.
Thanks for the tip.


as2 wrote:
> 
> Reading or RMWing  the ports anywhere else in the program may cause 
> problems, 
> ...
> 
Yes I already had such problems; I would say "will cause problems"; that's 
a certitude.
If I need it I use only the shadow reg that is read in int routine...


as2 wrote:
> 
> Is the change 'glitch' you get when the pin changes in a cycle where you
> read the port enough to set the interrupt flag? I don't know. 
> 
I'm not sure too... I think I have to be resolved to experiment.

That said, I don't understand why they have latched with Q3 at pin level.
In other hardware that I saw, there is a simple xor gate between input 
signal and the last read, the outputs are ORed and this latches the whole
byte and sets int flag. That works fine and does not consume more silicon...


-----
Best regards,

Philippe.

http://www.pmpcomp.fr Pic Micro Pascal for all! 
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