On Wed, 15 Apr 2009 00:09:02 -0500, you wrote:

>Hi All,
>
>    I seem to get a lot of noise (measuring 1.9Vp-p with an antenna, uh, 
>I mean a scope probe) on the Vddcore pin when switching a lot of I/O at 
>once.  The PIC32MX440F512 is running at 80MHz, and I'm switching 12 I/O 
>lines on portd all at once at around 2MHz for testing purposes.  There 
>is a clear correlation of the noise to the I/O switch.  I've got a 0.1uF 
>ceramic in parallel with a 10uF LESR tantalum (0.9ohms) on the Vddcore 
>line, and the total distance from the cpu to the caps is around 400 
>mils.  Any suggestions on either rounding the outputs off a little or 
>should I try switching a single pin at a time (incredibly slow), or 
>changing the filter or it's location wrt the cpu on Vddcore?  I believe 
>that the noise on this line is causing some unintended POR resets, but 
>I've got the same looking Vddcore noise on two boards and only one 
>resets (showing POR as the source) so I'm not sure.

I've just read a a Xilinx appnote about decoupling which said that at higher frequencies, lower
value caps are more effective than 100nfs due to lower inductance
http://www.xilinx.com/support/documentation/application_notes/xapp623.pdf

Simultaneous switching always increases noise and possibly ground bounce - the latter may be the
cause of your resets - even switching half at a time may help a lot. Adding series Rs to the lines
close to the pins will also help reduce the effect of switching the capacitive load of the tracks.

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