I am working on a couple of PIC18F series boards using ICD2 for debug and
program downloads.

PIC18F67J50 based custom design with 8 digital ins (PORTD) and 8 digital
outs (PORTE)
PIC18F97J60 based PICDEM.net 2 prototype board from MicroChip with 4 digital
ins (PORTB) and 8 digital outs (PORTJ)

While downloading new code onto both the boards using the ICD 2 debugger in
both debug and program mode, the outputs seem to be highly unstable - LEDs
connected to the outputs seem to flash while the program downloads.

This is highly undesirable in the industrial realtime application of the
boards as controllers where I dont want a field reprog of the chip using the
ICD 2 to operate machinery randomly!

Has anyone had similar problems? can anyone explain why this is happening?
Seems to happen for sample code (TCPIPStack) thats provided for the
PICDEM.net 2 board as well so its more of a PIC + ICD2 issue rather than a
coding issue?

I do realize the target chip memory maybe used by the ICD - have tried a
variety of code and changing memory linker maps but to no avail. The output
only fluctuates at innitial programming.. when the output window displays:

Programming Target...
...Validating configuration fields
...Erasing Part
...Programming Program Memory (0x0 - 0x9F7F)
Verifying...
...Program Memory
...Verify Succeeded
Programming Configuration Bits
.. Config Memory
...Verify Succeeded
...Programming succeeded
16-Jan-2009, 13:51:29

I realize this is only for a short duration and is perhaps inevitable while
programming target in a development/testing environment but I need to know
WHY this is happening as the PIC will be used as an industrial controller
and we need to rectify this as it will have adverse effects while writing
new code in the field (i.e. with the outputs going live uncontrollably
during download!). 

Since I am still learning, you will have to be slightly patient with me.
Included below at the bottom of this message are the configuration bits I am
using in the code.

CLK is actually software controlled and the CLK0 and CLK1 are manipulated
using the FOSC bit which is set to HSPLL. The tick is then manipuilated
inside the code at every cycle, if you know what I mean.

VPP or MCLR in this case is not manipulated in anyway in my code.

DAT and VPP Im not too sure about as I cant find them in the datasheet but
if I can impose upon you to visit the datasheet of this demo board at:
http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1406&dDocName=en028217

You will see that I am communicating with the board using RB7 and RB6 on the
J4 (in the schematic). This means most settings are set using software since
the board ready-developed kit.

The RB pins are manipulated in my code the folloing way for IO from the
inputs from RB0-RB3 (the 4 push buttons).

(in an init function call)
elif defined PROCESSOR_PIC18F97J60_CONTROLLER_PICDEM2
   // Inputs
   TRISB = 0xFF;

(in a different function call to load from inputs)
#if defined PROCESSOR_PIC18F97J60_CONTROLLER_PICDEM2
   inp = PORTB;

(specfic PORTB bits also manipulated in every loop)
void init_address(void)
{
   UINT8 delay = 100;

   // Enable address switch
   PORTBbits.RB4 = 1;

   // Arbitrary settling time
   while (delay--);

   // Read the address switch
   MODULE_ADDRESS = (PORTA & 0x0F);
   // Disable the address switch
   PORTBbits.RB4 = 0;

   MASTER = TRUE;
   // If address is non-zeo, this module is a slave
   if (MODULE_ADDRESS)
   {
       MASTER = FALSE;
   }
}


(config bits file)
// The following configuration should be used for development (i.e. WDT =
OFF, DEBUG = ON):
   
   // CONFIG1H
   #pragma config CP0 = OFF                        // Code protection off

   // CONFIG1L
   #pragma config DEBUG = OFF                        // Background debugging
on
   #pragma config XINST = ON                        // Extended instruction
set on
   #pragma config STVR = ON                        // Stack over/underflow
reset enabled
   #pragma config WDT = OFF                        // Watchdog Timer off
  
   // CONFIG2H
   #pragma config WDTPS = 32768                    // Watchdog Timer divider
= 32768
  
   // CONFIG2L
   #pragma config IESO = OFF                        // Two-speed startup
disabled
   #pragma config FCMEN = OFF                        // Fail-safe Clock
Monitor disabled
   #pragma config FOSC = HSPLL                        // Oscillator set to
HSPLL
  
   // CONFIG3H - different for PIC18F97J60
   //#pragma config ETHLED = ON                    // MSSP 7-bit Address
masking
   //#pragma config MSSPMSK = MSK7                    // MSSP 7-bit Address
masking
   //#pragma config PMPMX = ON                        // PMP pins placed on
EMB (80 pin devices only)
   //#pragma config ECCPMX = ON                    // ECCP1 outputs to RE6&5
ECCP3 outputs to RE4&3 (80 pin devices only)
   //#pragma config CCP2MX = DEFAULT                    // ECCP2 outputs to
RC1
  
   // CONFIG3L
   //#pragma config WAIT = ON                        // External Bus wait
states off (80 pin devices only)
   //#pragma config BW =    ON                        // External Bus width
= 16 bits (80 pin devices only)
   //#pragma config EMB1 = ON                        // External Bus... (80
pin devices only)
   //#pragma config EMB0 = ON                        // ...disabled (80 pin
devices only)
   //#pragma config EASHFT = ON                    // External Address Bus
shifted to 0000 (80 pin devices only)


Thanks and hope you can shed some light on my vows!

Best regards,

Kashan 
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