Alan B. Pearce wrote:

> As a side issue of this, do the newly announced chips with the extended 
> instructions have a deeper stack? 
> 

See : http://ww1.microchip.com/downloads/en/DeviceDoc/41364A.pdf

 From the rellevant sections :

 > 2.4 Stack
 > All devices have a 16-level x 15-bit wide hardware
 > stack (refer to Figures 2-1 and 2-3).

 > 2.4.1 ACCESSING THE STACK
 > The stack is available through the TOSH, TOSL and
 > STKPTR registers. STKPTR is the current value of the
 > Stack Pointer. TOSH:TOSL register pair points to the
 > TOP of the stack. Both registers are read/writable. TOS
 > is split into TOSH and TOSL due to the 15-bit size of the
 > PC. To access the stack, adjust the value of STKPTR,
 > which will position TOSH:TOSL, then read/write to
 > TOSH:TOSL. STKPTR is 5 bits to allow detection of
 > overflow and underflow.
 >
 > During normal program operation, CALL, CALLW and
 > Interrupts will increment STKPTR while RETURN and
 > RETFIE will decrement STKPTR. At any time STKPTR
 > can be inspected to see how much stack is left. The
 > STKPTR always points at the currently used place on
 > the stack. Therefore, a CALL or CALLW will write the
 > PC and then increment the STKPTR, and a return will
 > decrement the PC and then unload the PC.

 > 2.4.2 OVERFLOW/UNDERFLOW RESET
 > If the STVREN bit in Configuration Word 2 is
 > programmed, the device will be reset if the stack is
 > PUSHed beyond the sixteenth level or POPed beyond
 > the first level, setting the appropriate bits (STKOVF or
 > STKUNF, respectively) in the PCON register.
-- 
http://www.piclist.com PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist