> To interface with such DIMMs, an FPGA or CPLD would help a lot. I
> could see there being some applications (such as a digital scope or
> fast datalogger) which would still benefit from a deep fast RAM buffer
> before dumping to flash at a slower rate.

Hmmm, there's a thought. I made an analyser using discarded fast cache
memory. 4 x 8k x 8 I think it was, without having a rummage. This was
long ago when -10 PICs were all the rage and the data was dumped through
LPT1: to a GWBASIC program. Still, worked OK and solved more than
one head-scratcher problem

A PIC-based DIY logic analyser would make a good public domain project,
but I'd guess there'd be more than one already out there. Don't know if there's
an analogue one though, that would be at least as useful


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