Seeing that some of the pc based logic analyzers are slow or small (like the 
parallel port-with-only-a-buffer homebrew types), If one had a pic design that 
was synchronous with the external hardware (same clock), or asynchronous 
circuitry that didn't depend on timing at all from the pic, what would be the 
cons in slowing the pic clock down to whatever freq would make tracing easy? 
Would dropping from 10MHz to 10kHz be too much?

It obviously wouldn't show race conditions, capacitive loading effects, etc, 
but even then, if the problems went away at slow speed and not at high speed it 
would be telling. Does anyone do this? Any problems? If so, is it useful for 
comm too, only scaled slower, out of the pic (as in SPI and such)?

-Skip

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