>>> bcf INTCON,GIE >>> movfw shadow >>> movwf PORTx >>> bsf INTCON,GIE >>> >>> The interrupt latency will increase at most by 3 TCy. >>> >> True, but that sequence works only if interrupts were disabled at the >> start. >> > If you analyze it well, you may notice that this will work, because the > bsf is atomic and the ISR must use the shadow the same way the main > routine does (without the interrupts disabling/enabling of course). What I meant was that the sequence enables interrupts, even when interrupts were initially disabled. Hence it is not Ok for a general-purpose 'flush the shadow to the port' routine. -- Wouter van Ooijen -- ------------------------------------------- Van Ooijen Technische Informatica: www.voti.nl consultancy, development, PICmicro products docent Hogeschool van Utrecht: www.voti.nl/hvu -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist