Wouter van Ooijen escreveu:
>> bsf shadow,0
>> bcf INTCON,GIE
>> movfw shadow
>> movwf PORTx
>> bsf INTCON,GIE
>>
>> The interrupt latency will increase at most by 3 TCy.
>>     =

>
> True, but that sequence works only if interrupts were disabled at the =

> start.
>   =

If you analyze it well, you may notice that this will work, because the
bsf is atomic and the ISR must use the shadow the same way the main
routine does (without the interrupts disabling/enabling of course).

If the ISR sets/clears any pin other than the one changed by the main
routine, it will just commit the change made by the main routine.

If the ISR changes the same pin to the opposite value, then you will
lose a "glitch" in the pin (the main routine would have set the pin and
the ISR would immediately clear it). If you really need this "glitch",
then you need to disable the interrupts one instruction earlier.

For most applications, such "glitch" is not useful (sometimes it is
nasty indeed). LEDs, Relays, Motors and the like are better off without
the glitch.

For inter-devices communication, one may need it, but I would hardly
depend on such a indeterministic approach. Unless you are really
tweaking things (if you know exactly when the interrupt is going to
occur, to generate a precisely timed pulse for instance), there are
better options.

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