have a look at this site, its a good place to get ideas when starting, http://www.fpga4fun.com/digitalscope. html the development boards are very cheap and the example code is very well explained. the scope front end is quite close to what you need you probably just need an external frame buffer, how large is your frame? and what is the required frame rate? Richard Listas de Correo wrote: > actually, what I want to implement is a frame grabber, I think that is > the name for it. > > Once a user or a sub-system requires the capture, the whole system > will wait for a pulse synchronized with the frames. > > When I have this pulse, I start sampling for a given time at a given > frequency (up to 150MHz) The idea is to use the FPGA or whatever as a > simple bridge between the ADC and the RAM, then, when the one frame > sample is finish, use a FT245 (parallel USB transceiver) to txmit the > data over the USB port to the PC application... > > would that be as easy as it sounds? > > Regards > > On Mon, Oct 20, 2008 at 11:16 PM, Sean Breheny wrote: > >> I just want to warn you based on some recent experience that making an >> FPGA design work reliably is not easy. Using one is not like >> programming a microcontroller, it is more like designing a circuit. I >> don't know your experience level, but you did say that you've never >> used an FPGA before. This might not be the best project to use for >> learning as it is fairly challenging. I'd recommend that you get a >> demo board and play around with some easier stuff first. >> >> As one example of a gotcha, I wrote VHDL which implemented motor >> driver logic on a Lattice Semi FPGA. Part of it included a keepalive >> detector which would shut down the motor if a 50Hz signal (+/- 10%) >> was not present on one pin. Everything seemed to be working great with >> the first prototype. Then I made several test units and ran them for a >> while. Once in a blue moon, one or two of the units would decide >> momentarily that the 50Hz signal was absent when it wasn't. The >> problem was also temperature dependent. >> >> In the design, my main clock was 1MHz. To make the numbers smaller in >> the 50Hz decoder, I ran the 1MHz clock through a divide by 100 unit >> (in the FPGA) to produce a 10kHz clock for the 50Hz decoder module. >> Because the 1MHz clock was routed through primary clock routing >> resources and the 10kHz clock passed through a functional block first, >> their edges could drift apart by a few nanoseconds. This was enough to >> cause some logic pathology by circuits which were synchronous to the >> 1MHz clock and which checked the output of the 50Hz module, or perhaps >> problems with 1MHz-clock-sync'd signals entering the 50Hz module. It >> was something like metastability. I had to fix it by running >> everything directly from the 1MHz clock. >> >> There are tools to check timing inside the FPGA and the FPGA's >> internals are well spec'd, so it isn't as hard as, say, designing most >> analog circuits, but it isn't as easy as micro programming, either. >> >> It also takes a while to get your head around VHDL or Verilog. They >> work like programming languages but they aren't really. They are a >> means for describing what you want the FPGA to do, but the way you >> structure your logic will alter how it gets implemented in important >> ways. >> >> Sean >> >> >> On Mon, Oct 20, 2008 at 9:54 PM, Xiaofan Chen wrote: >> >>> On Tue, Oct 21, 2008 at 6:44 AM, Listas de Correo wrote: >>> >>>> Hi, I need to make a device that will have to capture one frame of a >>>> non standar video signal and store it in RAM, then pass that info to a >>>> PC trough USB. >>>> The signal should be sampled at 150MHz maximum. >>>> >>>> We are considering using an FPGA, but since we never used one, we dont >>>> know were to begin. I think the Cyclone III would be a good choice, >>>> but any information that someone experienced can provide would be >>>> really appreciated. >>>> >>> I do not know too much about FPGA (other than knowing that it is >>> getting more and more important). But last year I attended the >>> Xilinx/Avnet X-Fest seminar and it seems that typically this is >>> done with higher-end FPGA like Virtex 4/5. >>> Reference for the X-Fest: >>> http://www.fpgajournal.com/news_2007/08/20070815_01.htm >>> >>> Xiaofan >>> -- >>> http://www.piclist.com PIC/SX FAQ & list archive >>> View/change your membership options at >>> http://mailman.mit.edu/mailman/listinfo/piclist >>> >>> >> -- >> http://www.piclist.com PIC/SX FAQ & list archive >> View/change your membership options at >> http://mailman.mit.edu/mailman/listinfo/piclist >> >> -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist